CryptoNAS: Private Inference on a ReLU Budget
Zahra Ghodsi, Akshaj Veldanda, Brandon Reagen, Siddharth Garg
arXiv preprint

SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks
Maria I. Mera Collantes, Zahra Ghodsi, Siddharth Garg
IEEE VLSI Test Symposium (VTS), May 2020

Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators
Jeff Zhang, Zahra Ghodsi, Siddharth Garg, Kartheek Rangineni
IEEE Design & Test, Oct 2019

Outsourcing Private Machine Learning via Lightweight Secure Arithmetic Computation
Siddharth Garg, Zahra Ghodsi, Carmit Hazay, Yuval Ishai, Antonio Marcedone, Muthuramakrishnan Venkitasubramaniam
NeurIPS Workshop on Privacy Preserving Machine Learning (PPML), Dec 2018

Thundervolt: Enabling Aggressive Voltage Underscaling and Timing Error Resilience for Energy Efficient Deep Learning Accelerators
Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg
Design Automation Conference (DAC), June 2018

Safetynets: Verifiable Execution of Deep Neural Networks on an Untrusted Cloud Zahra Ghodsi, Tianyu Gu, Siddharth Garg
Advances in Neural Information Processing Systems (NeurIPS), Dec 2017
[video] [code]

Optimal Checkpointing for Secure Intermittently-powered IoT Devices
Zahra Ghodsi, Siddharth Garg, Ramesh Karri
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 2017

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